8086 Microprocessor competitive bits 2

MULTIPLE CHOICE QUESTIONS ON “SIGNAL DESCRIPTIONS OF 8086”

1. The clock rate of microprocessor 8086 is _________.

a) 5 MHZ

b) 8 MHZ

c) 10 MHZ

d) All of the mentioned

Answer: d
Explanation: The microprocessor 8086 is a 16-bit CPU available in three clock rates i.e. 5, 8 and 10MHz.

2. In which T-state does the CPU sends the address to memory or I/O and the ALE signal for demultiplexing ­­­­­­________.

a) T1

b) T2

c) T3

d) T4

Answer: a
Explanation: During the first clocking period in a bus cycle, which is called T1, the address of the memory or I/O location is sent out and the control signals ALE, DT/R’ and IO/M’ are also output.

 3. BHE of 8086 microprocessor signal is used to interface the_____

a) I/O

b) DMA

c) Even bank memory

d) Odd bank memory

Answer: d
Explanation: If BHE’=0, then it indicates the transfer of data over the higher order data bus i.e. D₈-D_15.  The higher order bus is interfaced to odd address bank memory when BHE’ is enabled.

4. Ready pin of a microprocessor is used______

a) To indicate that processor is ready to receive inputs outputs

b) To indicate that processor is ready to receive inputs output

c) To introduce wait states

d) To provide direct memory access.

Answer: c
Explanation: This input is controlled to insert wait states into the timing of the microprocessor.

5. The pins of minimum mode AD0-AD15 have _____ address and ____ data bus.

a) 16, 8

b) 16, 16

c) 8, 16

d) 8, 8

Answer: b
Explanation: The microprocessor 8086 has 20 address lines and 16 data lines. Out of 20 address lines, 16 address lines are time multiplexed with data lines AD0-AD15.

6. The function of pins from 24 to 31 depend on the mode in which ____ is operating.

a) 80386

b) 80387

c) 8085

d) 8086

Answer: d
Explanation: The 40 pins of 8086 are divided into 3 categories. i. Common mode signals                          ii. Minimum mode signals and iii. Maximum mode signals. Pin no’s 24 to 31 are different in 8086 when it is operating in maximum mode or in minimum mode.

7.  The _______ input is examined by a ‘wait’ instruction.

a) K

b) TEST

c) LOC

d) KIT

Answer: b

Explanation: TEST’ input is examined by WAIT instruction. When TEST’ goes low, execution will continue, else, the processor remains in an idle state.

8. After reset execution starts form _______.

a) 00000H

b) FFFF0H

c) FFFFFH

d) 003FFH

Answer: b
Explanation: After reset processor starts execution from FFFF0H location where the processor initialization codes are available.

9.  If there is an edge triggered input at NMI Pin causes_____ Interrupt.

a)  Type-0

b)  Type-1

c) Type-2

d) Type-3

Answer: c
Explanation: 8086 microprocessor has 256 software interrupts. INT00 to INT FF or Type-0 to Type-255. Non maskable interrupt is also called as INT 2 or TYPE-2 interrupt.

10.  If MN/MX is low, the 8086 operates in _____ mode.

a) Minimum mode

b)  Maximum mode

c)  Both A and B

d) Control mode

Answer: b
Explanation: If MN/MX’ is tied to Ground, the 8086 operates in maximum mode and MN/MX’ is tied to Vcc, the processor 8086 operates in minimum mode.

11. The RD, WR, M/IO is the heart of control for a _______ mode.

a) Minimum mode

b)  Maximum mode

c)  Both A and B

d) Control mode

Answer: a
Explanation: The minimum mode signals are HOLD, HLDA, WR’, M/IO’, DT/R’, DEN’, ALE, INTA’.

12. If S’₂ =0, S’₁ =1, S’₀ =1, what is the status of the microprocessor?

a) Interrupt acknowledge

b) Read I/O port

c) Write I/O port

d) Halt

Answer: d
Explanation:  Based on the status lines we can examine the state of processor.

13. Which of the following processor supports pipelined architecture?

a) 8080

b) 8085

c) 8086

d) 8008

Answer: c
Explanation: 8086 microprocessor supports pipelined architecture because of its predecoded instruction byte queue; it can fetch the next instruction while executing the current instruction. 

14. In order to initiate the fetch cycle by BIU atleast _______ bytes of the queue must be empty.

a) 1

b) 2

c) 3

d) 4

Answer: b
Explanation: The queue is updated after every byte is read from the queue but fetch cycle is initiated by BIU only if atleast 2 bytes of the queue are empty and the EU concurrently executing the fetched instructions.

 MULTIPLE CHOICE QUESTIONS ON “PHYSICAL MEMORY ORGANIZATION”, “GENERAL BUS OPERATION”,” I/O ADDRESSING CAPABILITY”, “SPECIAL PROCESSOR ACTIVITIES”

1. _______locations are reserved for operation including jump to initialization programme and I/O processor initialization.

a) 00000-07FFFH

b) 00000-003FFH

c) 00000-FFFFFH

d) FFFF0-FFFFFH

Answer: d
Explanation: In the 1MB of memory certain locations are reserved for specific CPU operations. The locations from FFFF0H-FFFFFH are reserved for operations including jump to initialization programme and I/O processor initialization.

2. _______ locations are reserved for interrupt vector table.

a) 00000-07FFFH

b) 00000-003FFH

c) 00000-FFFFFH

d) FFFF0-FFFFFH

Answer: b
Explanation: In the 1MB of memory certain locations are reserved for specific CPU operations. The locations from 00000H-003FFH are reserved for Interrupt vector table. 8086 has 256 vector interrupts and each interrupt is allocated 4 bytes of memory, therefore 256*4= 1024bytes i.e. 003FF.

3. A Maximum of ______ I/O devices can be interfaced with the CPU.

a)  64 Kbytes

b) 32 Kbytes

c) 16 Kbytes

d) 1 M byte

Answer: a
Explanation: The 8086 processor can address up to 64KB I/O byte registers. This means that a maximum of 64 KB I/O devices may be accessed by the CPU.

4. _________ register is used as 16-bit I/O address pointer.

a) AX

b) BX

c) CX

d) DX

Answer: d

Explanation: The 16-bit register DX is used as 16-bit I/O address pointer, with full capability to address up to 64K devices. 

  

5. After RESET, What will be the contents of CS and IP registers?

a) 0000H and 0000H

b) F000H and FFF0H

c) FFF0H and F000H

d) FFFFH and FFFFH

Answer: b
Explanation: After RESET execution starts from FFFF0H. During this period, all the internal register contents are set to 0000H except CS is set to value F000H and IP to value FFF0H.

6. For TEST signal to be accepted, it must be low for atleast______ clock cycles.

a) 3

b) 4

c) 5

d) 6

Answer: c
Explanation: For the TEST’ signal to be accepted, it must be low for atleast 5 clock cycles. If TEST’ is 0, then the processor is in running state.

7. Byte data with even address is transferred on _________ data bus lines.

a) D0-D7

b) D8-D15

c) D0-D15

d) All of the mentioned.

Answer: a
Explanation: Out of 16 data lines, the lower order data lines D0-D7 are interfaced to even address memory bank and the higher order data lines D8-D15 are interfaced to odd address memory bank.

MULTIPLE CHOICE QUESTIONS ON “MACHINE LANGUAGE INSTRUCTION FORMATS”

1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned

Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the operation code field.

2. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned

Answer: c
Explanation: Machine language instruction format has both the fields.

3. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes

Answer: b
Explanation: This format is only one byte long.

4. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes

Answer: a
Explanation: this format is 2 byte long.

5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operand
d) all of the mentioned

Answer: d
Explanation: The LSBs (least significant bits) from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other operand.

6. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned

Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of operation.

7. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit

Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.

8. If W-bit value is ’1′ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits

Answer: c
Explanation: If W-bit is ’1′ then the operand is of 16-bits, and if it is ’0′ then the operand is of 8-bits.

9. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned

Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution.

10. The instructions that transfer the control to some predefined address or the address specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned

Answer: b
Explanation: the control transfer instructions transfer control to the specified address.

11. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions

Answer: d
Explanation: the JUMP instruction transfers the control to the address located in the instruction.