VLSI

The list IEEE projects below are solved with more better results and the outputs are very accurate. To get the details of the modified projects of below, see the address at the end of the post

LIST OF PROJECTS WITH VERIFIED OUTPUTS:

VLSI (VERILOG/VHDL)

1. Convolution Encoder and VITERBI Decoder Using SOPC for Variable Constraint Length.

      Abstract: Convolution encoder and Viterbi decoder are the basic and important blocks in any Code Division Multiple Accesses (CDMA). They are widely used in communication system due to their error correcting capability But the performance degrades with variable constraint length. In this context to have detailed analysis, this paper deals with the implementation of convolution encoder and Viterbi decoder using system on programming chip (SOPC). It uses variable constraint length of 7, 8 and 9 bits for 1/2 and 1/3 code rates. By analyzing the Viterbi algorithm it is seen that our algorithm has a better error rate for ½ code rates than 1/3. The reduced bit error rate with increasing constraint length shows an increase in efficiency and better utilization of resources as bandwidth and power.

Keywords-convolution encoder; Viterbi decoder; SOPC; constraint length

Conclusion:  With no noise, input and output data is identical after encoding and decoding.With over noise, bit error rate changes. It is triple for 8 bit and reduces to half for 9 bit.The reduced bit error rate with increase in constraint length shows an increase in efficiency and better utilization of resources as bandwidth and power. In all larger constraint lengths are required for the extremely low error probabilities at high rates.In Satellite Communication, Turbo codes are being used and this can be replaced. In Satellite communication, convolution codes can be used as they have high error correction capability and high accuracy. Future scope indicates testing of convolution encoder and Viterbi Decoder with more than 9 bit constraint length. Space and satellite communication: there is plenty of  bandwidth that allowed for the use of  low spectral efficiency codes.

Low Power VLSI (Tanner tools v 13 and HSPICE)

2. Comparative performance analysis of low power full adder design in different logics in 22nm scaling technology.

Abstract: Our main objective in this work is to design of full adder with low power, high speed for extended frequency ranges. In previous proposed full adder circuits with good power delay product are designed and verified for the extended frequency operations. Power delay product values are obtained. In this work, we design EX-OR/EX-NOR Nodes to operate with low power delay, low operating voltage with full voltage swing. From this EX-OR/EXNOR a better optimized circuit is designed using transmission gate logic which operates at low power. The proposed circuit shows the best optimized results compared to previous works even in small scaling technologies we design and analyse the circuits in 22nm scaling technology, it is stimulated using Tanner tools V.13. The power

and delay results are calculated using H-SPICE tool.

Keywords: Single gate, double gate, Transmission gate, power delay product.

Conclusion: Here by we would like to conclude our proposed full adder circuit dissipates low power with low delay without any degradation in performance. From the above simulation results when the circuit is operated without any load in 22nm both the power dissipation and power delay product

are reduced by 10 times. Also in different frequency of operations the modified full adder can be operated at low voltages. The single gate and double gate MOSFET cannot be operated below 500MHz.

3. Implementation of power gating technique in CMOS Full Adder cell to reduce leakage power and ground bound noise for mobile application.

Abstract— Adder is the paramount circuit for many complex arithmetic operations. The adder cells mainly focus on reduction of power and increasing of speed. For mobile applications, designers work within a limited leakage power specification in order to meet good battery life. The designers apart from leveling of leakage current to ensure correct circuit operation also focuses on minimization of power dissipation. The power reduction must be achieved without comprising performance which makes it hard to reduce leakage current during normal operation of mobile. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper will focus on reducing sub threshold leakage power consumption and ground bounce noise during the sleep to active mode transition. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. We will perform analysis and simulation of various parameters such as standby leakage power, active power, ground bounce noise and propagation delay using Cadence Spectre 90nm standard CMOS technology.
Index Terms— cell, Ground bounce noise, Leakage power, Stacking power gating, Sleep transistor.

CONCLUSION:
In this paper 1-bit full adder cell with power gating technique is implemented where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. For optimal performance, stacking power gating technique has been implemented where SELECT input to stacked sleep transistor with delta T delay further minimizes the leakage power and ground bounce noise. The comparison of active power, standby leakage power is done and it’s observed that power is greatly reduced as we move from conventional CMOS full
adder cell to Modified Design2. The leakage power is reduced by 79 % (Design1), 85% (Design2) and 92% (Design2 with stacking power gating) in comparison to the conventional 1 bit full adder cell. Active power is reduced by 35.47% (Design1), 66.31% (Design2) and 59.48% (Design2 with stacking power gating) in comparison to conventional 1 bit full adder cell. The ground bounce noise is compared for Modified Design2 without delay and with delay and it is reduced in the latter case. The implemented 1-bit full adders are designed using 90nm technology and operated supply voltage of 1V.

4. Performance Analysis of Power Gating designs in Low Power VLSI Circuits

Abstract --- The growing market of mobile, battery powered electronic systems (e.g., cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. As density and complexity of the chips continue to increase, the difficulty in providing power dissipation might limit the functionality of the computing systems. Especially, at nanometer level the power dissipation consumes about 35% of the chip power. The purpose of this project is to analyse the performance of one of the most trustful approaches to low power design called as "Power Gating". The focus is only on CMOS devices in nanometer scale, as this technology is being the most widely adopted in current VLSI systems. In this project, we compare the performance of various power gating designs using 65nm technology. In a power gating structure, a transistor with high threshold voltage (Vth) is placed in series with a low Vth device. The high Vth transistor is called as the Sleep Transistor. In the power gating structure, a circuit operates in two different modes. In the active mode, the sleep transistors are turned ON and can be treated as the functional redundant resistances. In the sleep mode, the sleep transistors are turned OFF to reduce the leakage power. When a sleep transistor is placed at VDD, it is called as the "Header switch" and while it is placed near the ground, it is called as "Footer switch". In this project, I have taken the footer switch exclusively for all my designs.

Keywords- BCD Adder, Sleep transistors, distributed sleep transistor network (DSTN), Clock gated power gating, Sleep transistor Scheduling. 

CONCLUSION

Sleep transistor is designed at 65nm scale and implemented in power gating designs. The power gating designs discussed in this project are DSTN and Clock gating. The sleep transistors in each cluster is connected by means of daisy chain implementation which provides enough time for the results to propagate from one cluster to the other, thus synchronizing the circuit operation with triggering of sleep transistors. Clock gating method is introduced in power gating design, which provides additional control over the excitation process of sleep transistors. Finally, the performances of the DSTN and Clock Gating are compared in terms of power consumption of the circuit and surge current. It is found from the results that the power gating design is more efficient than the DSTN circuits designed at 65nm scale.

5. Design of pulse triggered flip flop using pulse enhancement scheme.

Abstract: For the past several years, much progress has been made in Low power VLSI Design .In This paper ,a novel low-power pulse Triggered flip- flop design is presented. First, the pulse generation control logic an AND function, is removed from critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for saving. Various post layout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in four FF designs under comparison.

Keywords: Flip flop, low power and pulse-triggered

Conclusion

In this paper, the various Flip flop design like, ip-DCO, MHLLF and SCCER are discussed. These were been also designed in Wicrowind tool and those result waveforms are also discussed. The comparison table also added to verify the designed methods. With these all results SCCER performed better than ip-DCO and MHLLF designs.

Future work

To improve the performance design of the P-Flip flop, The Pulse enhancement scheme will be designed and also these results will be discussed with the existing pulse trigger Flip Flop.

6. Design of low power high speed VLSI adder subsystem.

Abstract - The design of adder subsystem is the most focused area in VLSI design of processing units. So far there are a variety of such adders like RCA, CSA, CLA and ETA. ETA is the Error Tolerant Adder and is the latest of the adders which has better performance when compared with the other adders in terms of power consumption, delay etc. Whereas the designs so far is by front end

tools that performs simulations with ideal parameters instead of real time conditions. So, here in this paper, the design is approached through backend tool under real time simulation conditions. The results showed that the adder performance in terms of accuracy, delay, size and with 70% lesser power consumption than that of the conventional CMOS adders.

Key terms: Back end, adder, cadence, ETA, Front end.

CONCLUSION

So far from the various types of adders we have known, this logic proves to be more promising and optimal in the field of application specific processing units. With the results obtained from improved

design and extensive simulation, these adders are effective to be implemented practically.

FUTURE WORK

In future we are going to implement this logic in multipliers and work on its performance improvement with different techniques in multiplication.

7. Adiabatic logic based Low power multiplexer and de-multiplexer.

Abstract— Minimizing power of digital circuits is always the first priority for VLSI designers. Following this trend, this paper presents a CMOS-based new design approach for a low power adiabatic 8:1 Multiplexer and 1:8 Demultiplexer. Some standard adiabatic logic styles like PFAL, ECRL, 2n2n2p are investigated, which are bettered by the proposed logic. The simulation is carried out in NI-Multisim software at 0.5 μm CMOS technology for frequency range 200MHz – 800MHz.

Keywords-Adiabatic logic, Multiplexer, Demutilplexer, PFAL, ECRL, 2n2n2p, power dissipation, power saving.

CONCLUSION: 

This paper primarily focuses on lowering the power dissipation. Logics for multiplexer and demultiplexer are proposed and the results indicate that they have lesser power dissipation than some standard adiabatic logic styles. Their percentage power saving indicates their supremacy over their counterparts. Moreover, in the proposed logic, the transistor count and the area per chip is also relatively lesser. The future scope of this work is that multiplexers and demultiplexers with higher number of input and output lines can be constructed by cascading the proposed ones.

CONTACT: engineeringtechhub@gmail.com 

Phone number: 9490389019

Note: Complete project costs 5000/- only. (conditions apply)

Some more projects will be added shortly in other domains too.