Switching Circuits and Logic Design: Week 2 : Assignment 2

        1. What does Moore’s law say?

a. The speed of the transistors shall increase exponentially over the years.

b. The number of transistors that can be packed in a chip shall increase exponentially over the years.

c. To keep the delay of the circuits constant, the number of transistors in a chip must double every 18 months.

d. None of these

Ans: b

2. The output of an AND gate will be 1 if

 a. At least one of the inputs is at 1.

 b. At most one of the inputs is at 0.

 c. An even number of inputs must be at 1.

 d. None of these

3.  The output of an exclusive-OR gate will be 0 if

 a. An even number of inputs are at 1.

 b. An odd number of inputs are at 1.

 c. All the inputs are at 1.

 d. All the inputs are at 0

4. What is meant by the noise margin of a logic gate?

 a. The range of input voltages that are treated as logic 0.

 b. The range of input voltages that are treated as logic 1.

 c. The voltage range between the logic 0 and logic 1 ranges in the input.

 d. None of these

5. Which of the following are true for MOS transistors?

 a. An nMOS transistor conducts when the gate input is at low voltage.

 b. An nMOS transistor conducts when the gate input is at high voltage.

 c. A pMOS transistor conducts when the gate input is at low voltage.

 d. A pMOS transistor conducts when the gate input is at high voltage

6. A 2-input CMOS AND gate will require

 a. 2 nMOS and 2 pMOS transistors

 b. 2 nMOS and 3 pMOS transistors

 c. 3 nMOS and 2 pMOS transistors

 d. 3 nMOS and 3 pMOS transistors

7. The number of CMOS transmission gates required to build a 4-to-1 multiplexer is ……………….

Ans: 6

8. If the input signals to a Mach Zehnder interferometer are denoted by X and Y, the output at the Bar Port can be represented by

 a. X.Y’

 b. X’.Y

 c. X.Y

 d. X + Y

9. Some of the advantages of all-optical implementation of logic gates are

 a. High speed

 b. Low power consumption

 c. No interference from electrical signals

 d. All of these

10. The implementation of an IMPLY gate using memristors require

 a. Three memristors

 b. Two memristors and one resistance

 c. Four memristors

 d. None of these