Note: Any queries for the answers can be discussed in discussion hub or simply comment on post.
1. Which of the following is not true for a sequential circuit
a. The circuit output depends only on the present inputs
b. The circuit output depends on the present state and the present inputs
c. The next state depends on the present state and present inputs
d. The next state depends only on the present state
Ans: a and d
2. Which of the following statements is/are true?
a. A flip-flop is a level-sensitive storage element
b. A latch is a level-sensitive storage element
c. A latch is triggered both at the positive as well as the negative edges of a clock.
d. A flip flop is triggered either at the positive edge or at the negative edge of a clock.
Ans: b and d
3.Why is S=R=1 considered an invalid input in a S-R flip flop?
a. The value of Q cannot be predicted when S=R=1 is applied.
b. The value of Q cannot be predicted when we apply S=R=0 after the application of S=R=1.
c. The circuit output starts oscillating.
d.None of these
Ans: b
4. The ON period of a clock signal is 10 nsec and the OFF period is 40 nsec. The frequency of the clock signal is ………… MHz.
Ans: 20
5. In the excitation table for J K flip flop, what do we have to apply on the J and K inputs to change the output value from 0 to 1?
a. J=1, K=X
b. J=X, K=0
c. J=X, K=1
d. None of these
Ans: a
6. The number of additional NAND gates required to convert a J-K flip-flop to a T flip-flop is ……….
Ans: 0
7. How many NAND/NOT gates are required to construct a J K master slave flip flop?
a.5
b.7
c.8
d.9
Ans: d
8. The hold time of a flip flop depends on:
a. The time period of the clock
b. The amount of time the input to the flip flop must be stable before the active clock edge appears.
c. The amount of time the input to the flip flop must be stable after the active clock edge appears.
d. None of these
Ans: c
9. The number of T flip-flops required to divide the frequency of a given clock signal by 64 is ………..
Ans: 6
10. What is meant by dynamic hazard in a combinational circuit in response to some changes in the input values?
a. There is a momentary transition in the output, but the initial and final output values are the same.
b. There is a momentary transition in the output, but the initial and final output values are the different.
c. There is a short circuit in the output that may lead to hazardous situation.
d. None of these.
Ans: b
1. Which of the following is not true for a sequential circuit
a. The circuit output depends only on the present inputs
b. The circuit output depends on the present state and the present inputs
c. The next state depends on the present state and present inputs
d. The next state depends only on the present state
Ans: a and d
2. Which of the following statements is/are true?
a. A flip-flop is a level-sensitive storage element
b. A latch is a level-sensitive storage element
c. A latch is triggered both at the positive as well as the negative edges of a clock.
d. A flip flop is triggered either at the positive edge or at the negative edge of a clock.
Ans: b and d
3.Why is S=R=1 considered an invalid input in a S-R flip flop?
a. The value of Q cannot be predicted when S=R=1 is applied.
b. The value of Q cannot be predicted when we apply S=R=0 after the application of S=R=1.
c. The circuit output starts oscillating.
d.None of these
Ans: b
4. The ON period of a clock signal is 10 nsec and the OFF period is 40 nsec. The frequency of the clock signal is ………… MHz.
Ans: 20
5. In the excitation table for J K flip flop, what do we have to apply on the J and K inputs to change the output value from 0 to 1?
a. J=1, K=X
b. J=X, K=0
c. J=X, K=1
d. None of these
Ans: a
6. The number of additional NAND gates required to convert a J-K flip-flop to a T flip-flop is ……….
Ans: 0
7. How many NAND/NOT gates are required to construct a J K master slave flip flop?
a.5
b.7
c.8
d.9
Ans: d
8. The hold time of a flip flop depends on:
a. The time period of the clock
b. The amount of time the input to the flip flop must be stable before the active clock edge appears.
c. The amount of time the input to the flip flop must be stable after the active clock edge appears.
d. None of these
Ans: c
9. The number of T flip-flops required to divide the frequency of a given clock signal by 64 is ………..
Ans: 6
10. What is meant by dynamic hazard in a combinational circuit in response to some changes in the input values?
a. There is a momentary transition in the output, but the initial and final output values are the same.
b. There is a momentary transition in the output, but the initial and final output values are the different.
c. There is a short circuit in the output that may lead to hazardous situation.
d. None of these.
Ans: b
where is assignment 8 solution
ReplyDelete