CMOS DIGITAL VLSI DESIGN: Assignment 8:

1. In presence of clock jitter (Tj), under worst case scenario, for proper operation of a synchronous sequential logic, the clock period reduces by

 Tj

 2Tj

 3Tj

 0.5Tj

Ans: b

2. Clock skew between two clocks is influenced by which of the following factor:

 Inductance of the interconnect from clock to the sequential block

 Capacitance of the interconnect from clock to the sequential block

 On chip local temperature

 None of the above

Ans: b

3. For clock skew and jitter the systematic error is

 Unpredictable

 Varies from one chip to other

 Cannot be modelled during design

 Predictable

Ans: d

4. The best way to avoid skew and jitter is

 Run clock and data in opposite direction

 Run clock and data in the same direction

 Have balanced clock loads

 Use symmetrical interconnect lengths

Ans: c

5. In a pipeline based sequential circuits, let us assume that we are using positive level triggered latches between combinational block, then which of the following statements is true

 The latches should be activated by CLK signal only

 The latches should be activated by CLK and CLK(bar) signals

 The latches should be activated by CLK(bar) signal only

 None of the statement is true

Ans: a

6. For a C2MOS pipelined circuit to be race free the essential condition is 

 All the logic function implanted should be non-inverting

 All the logic function implanted should be inverting

 The clock should be jitter and skew free

 Power fluctuation to be minimized

Ans: a

7. For a latch based clocking how many phase clock sequence is required

 Single Phase

 Three Phase

 Two Phase

 Four Phase

Ans: c

8. In a latch based clocking scheme if the first D-latch is active low and runs on a clock referred to as TCLK1, then the evaluation time for the combinational block next to the latch is

 2TCLK1

 TCLK1/4

 6TCLK1

 TCLK1/2

Ans: d

9. Not all clock event occur simultaneously in a system due to

 Clock Skew

 Clock Jitter

 Both Skew and Jitter

 None of these

Ans: c

10. Sense Amplifier in a conventional memory design allows 

 Full Rail-to-Rail Swing in the output

 Reduces the output transition time

 Increases the Noise Margin 

 Reduces the Noise Margin

Ans: a