CMOS DIGITAL VLSI DESIGN: Assignment 5

Which of the following statement is true for high impedance nodes ?
a. May be modeled as a open circuit
b. May be modeled as a closed circuit
c. These nodes can be verified by voltage measurement alone
d. They are not floating nodes

Ans: a

Assuming Wn and Wp to be widths of the NMOS and PMOS transistors of a Domino CMOS Logic, the value of tPHL (high-to-low propagation delay) is equal to
a. Wn/Wp
b. Wp/Wn
c. Zero
d. Wn + Wp

Ans: d ( doubt between C and D)

For a 180 nm process the value of the unit delay is approximately
a. 100 ps
b. 12 ps
c. 35 ps
d. 55 ps

Ans: b

If the output and the input capacitance of logic is Cout and Cin respectively then the value of electrical effort is
a. Cin /Cout
b. Cout /Cin
c. 2Cin /Cout
d. 2Cout /Cin

Ans: b

Find the value of the logical effort of a NOR-2 gate whose delay is equivalent to a CMOS inverter whose Wp/Wn = 3/1, where Wp and Wn are the widths of the PMOS and NMOS respectively
a. 5/3
b. 7/3
c. 11/5
d. 7/4

Ans: d

A NAND-2 gate drives a NOR-2 gate of equal dimensions and capacitive loading, then the logical effort of the compound network will be
a. 20/9
b. 25/3
c. 30/7
d. 35/7

Ans: a

For a three stage digital logic design using NAND, NOR and MUX, in series, the total parasitic delay is 8 unit and the best stage effort is 6. The total delay from primary input to output is
a. 27
b. 25
c. 26
d. 21

Ans: c

The frequency of an N stage ring oscillator with the following parameters: Logical effort = Branching Effort = Electrical Effort = parasitic delay = 1 units and delay = 3 units is
a. 1/4N
b. 4N
c. 6N
d. 1/6N

Ans: d

The time before the rising/falling clock edge till which the data must be stable for proper sampling of the data is referred to as
a. Set-up Time
b. Hold Time
c. Clock Period
d. Tc-q delay

Ans: a

Memories based on positive feedback falls under the class of
a. Astable Circuits
b. Bistable Circuits
c. Multivibrators
d. Dynamic Circuits

Ans: b