CMOS DIGITAL VLSI DESIGN: ASSIGNMENT 7

1. Cascading negative and positive latches will result in a 
 A. Master-Slave configuration
 B. Dynamic configuration
 C. Level Register
 D. One Shot generators

Ans: a

2. Using dual edge triggered latch, the frequency of operation is
 A. Halved
 B. One-fourth 
 C. Double 
 D. Quadrupled

Ans: c

3. At the metastable point in the Voltage Transfer Characteristics of two cascaded inverter, the voltage gain is ideally
A. Zero
 B. Infinity
 C. 100 V/V
 D. Cannot be determined 

Ans: b

4. The precondition for stability of a bi-stable circuit is
 A. The loop gain should be less than one at stable point
 B. The loop gain should be greater than one at stable point
 C. Loop gain should be equal to one at stable point
 D. Stability and Loop Gain has no relation at stable point

Ans: a

5. Te-q delay for the master slave edge triggered register using multiplexer would be 
 A. Tpd-tx+Tpd-inv
 B. Tpd-tx+2Tpd-inv
 C. 2Tpd-tx+Tpd-inv
 D. Tpd-tx+3Tpd-inv

Ans: a

6. The hold time for a Master-Slave positive edge triggered register using multiplexers is
 A. Delay of four transmission gates
 B. Delay of each static inverter
 C. Cannot be determined
 D. Zero

Ans: d

7. If the clock routing delay is Tpd and there are two non-overlapping clocks with nonoverlap time as Tnover, then for a proper functioning of a master-slave register based on pass transistor logic which of the following condition should hold good
 A. Tpd>Tnover
 B. Tpd<= Tnover
 C. Tpd<Tnover
 D. Tpd =>Tnover

Ans: c

8. For a dynamic transmission gate edge triggered register, the total delay from D to Q is equal to 
 A. Delay of two Transmission Gate
 B. Delay of two Transmission Gate and One Inverter
 C. Delay of two Inverters and One Transmission gate
 D. Delay of two Inverter

Ans: c

9. In which of the following logic style the CLK-CLK (bar) clocking is insensitive to overlap
 A. C2MOS
 B. NORA
 C. TSPC
 D. Pipeline

Ans: a

10. The condition for C2MOS to work as insensitive to clock and clock-bar overlap is
 A. Rise (fall) time should be greater than propagation delay of register
 B. Rise (fall) time should be lesser than propagation delay of register
 C. C2MOS is always insensitive to overlap behaviour
 D. None of the above

Ans: b