Verilog HDL: Programming Assignment

1) 

module full_adder ( a ,b ,cin ,sum ,carry );

output sum ;

output carry ;

input a ;

input b ;

input cin ;

  

assign sum = a ^ b ^ cin;  

assign carry = (a&b) | (b&cin) | (cin&a);

endmodule

module adder2bit ( A ,B ,Cin,Sum ,Cout );

  output [1:0] Sum ;

output Cout ;

  input [1:0] A ;

  input [1:0] B ;

  input Cin;

  wire w;

  full_adder u0 (A[0],B[0],Cin,Sum[0],w);

  full_adder u1 (A[1],B[1],w,Sum[1],Cout);

 

endmodule

2.) module full_adder ( a ,b ,cin ,sum ,carry );

output sum ;

output carry ;

input a ;

input b ;

input cin ;

  

assign sum = a ^ b ^ cin;  

assign carry = (a&b) | (b&cin) | (cin&a);

endmodule

module adder2bit ( A ,B ,Cin,Sum ,Cout );

  output [1:0] Sum ;

output Cout ;

  input [1:0] A ;

  input [1:0] B ;

  input Cin;

  wire w;

  full_adder u0 (A[0],B[0],Cin,Sum[0],w);

  full_adder u1 (A[1],B[1],w,Sum[1],Cout);

 

endmodule

module adder6 (A, B, CI, Result, CO);

   input [5:0] A, B;

   input CI;

   output [5:0] Result;

  output CO;wire[4:0] w;

  adder2bit u1(A[1:0],B[1:0],CI,Result[1:0],w[1]);

  adder2bit u2(A[3:2],B[3:2],w[1],Result[3:2],w[3]);

  adder2bit u3(A[5:4],B[5:4],w[3],Result[5:4], CO);

endmodule

3) 

module dlatch (D,En,Q);

  input D,En;

  output Q;reg Q;

  always @(D,En)

    if(En)

      Q<=D;

Endmodule

4) 

module dlatch4(D,En,Q);

  input En;

  input [3:0]D;

  output [3:0]Q;

  wire [3:0]Q;

  dlatch d1 (D[3],En,Q[3]);

  dlatch d2(D[2],En,Q[2]);

  dlatch d3(D[1],En,Q[1]);

  dlatch d4(D[0],En,Q[0]);

endmodule

         

module dlatch (D,En,Q);

  input D,En;

  output Q;reg Q;

  always @(D,En)

    if(En)

      Q<=D;

endmodule